1. Technical Field
This invention relates to data processing devices. In particular, this invention relates to a system and method for detecting the data bus width of a memory device.
2. Description of Related Art
Handheld data processing devices, sometimes known as “personal digital assistants”, are becoming very popular. Such devices have the ability to store a significant amount of data, including calendar, address book, tasks and numerous other types of data for business and personal use. Most handheld data processing devices have the ability to connect to a personal computer for data exchange, and many are equipped for wireless communications using, for example, conventional email messaging systems.
Cost and space are two significant limiting parameters in handheld data processing devices. As a general rule, reducing the number of chips required by the device also reduces the cost and size of the device, and in some cases energy consumption.
A typical handheld processing device has a processor for processing the data; a non-volatile memory storage device in the form of a NOR flash chip, and a volatile memory storage device such as SRAM. The NOR flash retains data when no power is being supplied to the chip, and the SRAM caches data from the flash memory during operation of the device. Accordingly, the processor in such handheld data processing devices is designed and configured to read data from and write data to SRAM and NOR flash memory devices.
Another available type of non-volatile memory, known as NAND flash, is less expensive and contains more memory than a comparable NOR flash device. However, whereas NOR flash memory is read and written to one byte or word or other device width at a time, like random access memory (RAM), NAND flash memory must be read and written to in blocks or “sectors” of data, like a disk drive. It is therefore not possible for an existing NOR flash type processor in a handheld data processing device to utilize a NAND flash memory, because the architecture of the processor requires that it process bytes of data rather than sectors. If a NAND flash were coupled to such a processor, not only would the processor be unable to process data during normal operation of the device, it would not be able to boot up because it would not be able to access the specific sequence of instruction bytes constituting the bootup routine. In order to reconfigure the processor to be able to boot and run using a NAND flash chip, the architecture of the processor would need to be drastically changed, which is an extremely expensive and laborious process.
It would accordingly be advantageous in such a device to provide a memory controller interface that supports NAND flash memory, to take advantage of the increased capacity and lower cost without having to redesign the main processor. Moreover, since NAND flash memory is available with either an 8-bit data bus or a 16-bit data bus, it would be advantageous to be able to use either form of NAND flash in the device, as circumstances may dictate. However, since the processor code—including the boot code—is stored in the NAND flash memory, the processor program code cannot be used to configure the data bus word size or “width,” because the data bus width must be determined before the processor code starts to run in order for the code to be accessed correctly when read out of NAND flash. In other words, the processor can only boot up from code stored in flash memory if the width of the data bus is known, so the memory controller can properly process the data as it is read out of the memory device.
It is possible to utilize a dedicated input pin to signal the data bus width. However, this requires additional space on the memory controller chip and complicates the circuit board topography.